Memory cells provided in a nonvolatile semiconductor memory device such as a NAND flash memory have a stacked gate structure in which a floating gate and a control gate are stacked with an interposed inter-gate insulating film.
The width of the floating gate becomes narrow and the upper portion of the floating gate becomes sharp as downscaling progresses.
In the case where the floating gate has such a form, the electric field concentration at the upper portion of the floating gate increases and a leak (an IPD (Inter-polysilicon dielectric) leak) occurs easily between the floating gate and the control gate.
Therefore, for example, there is a risk that programming defects and the like may occur because electrons that are injected into the floating gate during the programming may undesirably be emitted from the floating gate into the control gate.